Periodic digital signals are commonly used in a variety of electronic devices. Probably the most common type of periodic digital signals are clock signals that are typically used to establish the timing of a digital signal or the timing at which an operation is performed on a digital signal. For example, data signals are typically coupled to and from memory devices, such as synchronous dynamic random access memory (“SDRAM”) devices, in synchronism with a clock or data strobe signal. More specifically, read data signals are typically coupled from a memory device in synchronism with a read data strobe signal. The read data strobe signal typically has the same phase as the read data signals, and it is normally generated by the same memory device that is outputting the read data signals. Write data signals are typically latched into a memory device in synchronism with a write data strobe signal. The write data strobe signal should have a phase that is the quadrature of the write data signals so that a transition of the write data strobe signal occurs during a “data eye” occurring at the center of the period in which the write data signals are valid. The write strobe signal is typically generated by the memory controller from an internal clock signal that is derived from the system clock signal, and it is coupled to the memory device into which the data are being written. Unfortunately, the phase of the system clock signal is normally substantially the same as the phase of the write data signals. Therefore, it is necessary for the memory controller to generate the write data strobe signal as a quadrature signal having a phase that is 90-degrees relative to the phase of the internal clock signal. In other cases, a quadrature clock signal used for latching write data is generated in the memory device to which the data are being written. The quadrature clock signal is typically generated in the memory device from an internal clock signal that is also derived from the system clock signal.
Various techniques can be used and have been used by memory controllers and memory devices to generate a quadrature clock signal or write data strobe signal. If the frequency of the internal clock signal is fixed, a quadrature write strobe signal can be generated by a timing circuit that simply generates a transition of the write strobe signal a fixed time after a corresponding transition of the internal clock signal. However, synchronous memory devices are typically designed and sold to be operated over a wide range of clock frequencies. Therefore, it is generally not practical to use a fixed timing circuit to generate a write data strobe signal from the internal clock signal. Instead, a circuit that can adapt itself to an internal clock signal having a range of frequencies must be used.
Multi-phase clock signals are also required for applications other than for use as a write data strobe signal. For example, a “frequency doubler” circuit, which generates an output clock signal having twice the frequency of an input clock signal, can be implemented using an appropriate logic circuit that receives the input clock signal and quadrature versions of the input clock signal.
One conventional circuit that can generate multi-phase clock signals from an internal clock signal having a variable frequency is a delay-lock loop, such as the delay-lock loop 10 shown in FIG. 1. The delay-lock loop includes a tapped delay line 14 having four variable delay units (“VDUs”) 16, 18, 20, 22 coupled in series with each other. Each of the VDUs 16–22 has an input, an output, and a control input “C”. Each of the VDUs 16–22 couples a digital signal from its input I to its output with a delay corresponding to a delay control signal applied to its control input C. The input of the initial VDU 16 receives an internal clock signal iCLK. The outputs of all but the last VDU 22 is coupled to the input of the subsequent VDU 16–20. The output of each VDU 16–22 also forms a respective tap of the delay line 14 to provide four clock signals, CLK1–CLK4. As explained in greater detail below, the voltage-controlled delay provided by each of the VDUs 16–22 is composed of two components; a variable delay tv having a magnitude set by the control signal C and a fixed intrinsic delay ti, which is the minimum delay by which a signal can be coupled through the VDU. The delay D of each of the VDUs 16–22 is thus defined by the formula:D=DI+DV.The total delay DT of the delay line 14, i.e., the delay of the CLK4 signal relative to the iCLK signal, is thus given by the formula:DT=4DI+4DV.
The CLK4 signal generated at the output of the final VDU 22 is also applied to one of two inputs to a phase detector (“PD”) 26. The other input of the phase detector 26 receives the same iCLK signal that is applied to the input of the VDU 16. In operation, the phase detector 26 generates an error signal “E” at its output that is indicative of the lead or lag phase error of the CLK4 signal relative to the iCLK signal. The error signal E is applied to a VDU control unit 28, which generates a control signal that is applied to the control terminal C of the VDUs 16–22. The control signal adjusts the delay of the VDUs 16–22 to minimize the error signal and hence the phase error between the iCLK signal and the CLK4 signal. Therefore, the delays of the VDUs 16–22 are automatically adjusted until the phase of the iCLK signal is substantially equal to the phase of the CLK4 signal.
The operation of the delay-lock loop 10 will further be explained with reference to FIG. 2. The iCLK signal shown in the upper waveform is coupled through the first VDU 16 to produce the CLK1 signal shown in the second waveform of FIG. 2. The transition of the iCLK signal that produces the corresponding transition of the CLK1 signal are circled and linked to each other by a line in FIG. 2. Similarly, the indicated transition of the CLK1 signal is coupled through the VDU 18 to produce the indicated transition of the CLK2 signal, the indicated transition of the CLK2 signal is coupled through the VDU 20 to produce the indicated transition of the CLK3 signal, and the indicated transition of the CLK3 signal is coupled through the final VDU 22 to produce the indicated transition of the CLK4 signal. As previously explained, the delays of the VDUs 16–22 are automatically adjusted so that the iCLK signal has substantially the same phase at the CLK4 signal, which can be seen by comparing the iCLK signal shown in the top waveform of FIG. 2 to the CLK4 signal shown in the bottom waveform. All of the VDUs 16–22 are substantially identical to each other and they receive the same control signal so that they each provide the same delay. As can be observed from FIG. 2, since there are four VDUs 16–22 that together delay the iCLK signal by 360 degrees, each of the VDUs 16–22 delay the digital signal applied to its input by 90 degrees. The CLK1 signal thus has a phase of 90 degrees relative to the iCLK signal, the CLK2 signal thus has a phase of 180 degrees relative to the iCLK signal, the CLK3 signal has a phase of 270 degrees relative to the iCLK signal, and the CLK4 signal has the same phase as the iCLK signal.
The delay-lock loop 10 shown in FIG. 1 performs well over a wide range of frequencies in many instances. However, as will be explained with reference to FIGS. 3A and 3B, its high frequency range is limited by the intrinsic delay DI of each of the VDUs 16–22. With reference to FIG. 3A, as previously explained, each transition of the CLK4 signal is delayed from the corresponding edge of the iCLK signal by a total delay DT that is equal to the sum of the voltage-controlled delay VT and the intrinsic delay IT. Each of these delays VT and VI are shown in FIG. 3A. The period P of the iCLK signal is equal to the total delay, i.e., 4DV+4DI, and the frequency of the iCLK signal is the reciprocal of its period P, i.e., 1/(4DV+4DI). For example, if 4DV is equal to 4 ns and 4DI is equal to 1 ns, the frequency of the iCLK signal is 200 MHz, i.e., 1/(5* 10−9).
The delay lock loop 10 can continue to lock the CLK4 signal to the iCLK signal increases by simply reducing the magnitude of the voltage-controlled delay 4DV to reduce the total delay DT. However, as shown in FIG. 3B, as the frequency of the iCLK signal continues to increase, the voltage-controlled delay DV is eventually reduced to zero. At this point, the total delay DT can no longer be reduced because the intrinsic delay DI is fixed. The maximum frequency of the iCLK signal to which the CLK4 signal can be locked to using the delay-lock loop 10 is thus the reciprocal of 4DI. Using the above example in which the total intrinsic delay 4DI is 1 ns, the maximum frequency of the iCLK signal is 1 GHz.
The fixed intrinsic delay of delay lines used in conventional delay-lock loops can therefore severely limit the frequency range over which delay-lock loops can be used. There is therefore a need for a delay-lock loop having a frequency range that is not limited by the intrinsic delay of conventional delay lines.